Domestic EDA technology pioneer | PFTN semiconductor
Home
Products
Semiconductor Manufacturing Software
Process and Device Simulation (TCAD)
Optical Proximity Correction (OPC)
Design Enablement
Compact Modeling
Foundation IP
Solutions
Design Technology Co-Optimization
DTCO in logic technologies
Memory bitcell and array optimization
High-Reliability for Automotive and Aerospace
Soft-error: mechanism and design mitigation
Single Event Catastrophic Failure of Power Devices
FinFET Single Event Effects
Total Ionizing Dose Effect
Resources
Installer and Documents
TCAD Example Gallery
Blog
News
About Us
Company profile
Contact Us
Join Us
English
简体中文
Memory bitcell and array optimization
Billions and billions of densely packed bits
DTCO for memory bitcell and array optimization
Coming soon.
Sign In
Sign Up
Profile
NAME
The letter begins with a 3-12 length
PASSWORD
The value contains 6 to 12 letters and numbers
NEW_PASSWORD
The value contains 6 to 12 letters and numbers
E-MAIL
Invalid Email Address
TELEPHONE
This phone number format is not recognized
COMPANY/SCHOOL
This item cannot be empty
COUNTRY
This item cannot be empty
DESCRIPTION
This item cannot be empty
Sign Up
Send
Sign Out
Update
Save
Cancel
CONFIRM_PASSWORD
The value contains 6 to 12 letters and numbers
Confirm