Domestic EDA technology pioneer | PFTN semiconductor
Mozz TCAD : Process and Device Simulation
With the help of predictive computer simulations provided by Technology Computer-Aided Design (TCAD), device engineers and process-integration engineers may develop and optimize semiconductor processes and devices using fewer silicon cycles and wafers.
Mozz TCAD offers advanced model caliberation, design of experiment (DoE), and result visualization in the integrative GUI environment, which builds upon the underlying physics-based process and device simulators. Mozz TCAD provides connectivity to the circuit design flow, including layout-driven structure creation, RC parasitic extraction and TCAD-based compact modeling.
MoSiOPC : Lithography and Mask Synthesis
MoSiOPC provides an accurate the fast solution for the modeling lithography processes and the synthesis of photomasks from both dense and sparse designs.
It offers a complete GDS-to-Mask flow, consisting of model-based OPC correction and post-verification, rule-based biasing, sub-resolution assist feature (SRAF) insertion and mask rule checking (MRC).
Design Enablement: Compact Model and Foundation IP
Compact modeling is an essential step in modern IC design flow that links circuit design, device and processing technology. Our modeling tools and services cover a wide range of devices and technologies, including CMOS, RF, BCD, discrete power, and emerging technologies like GaN and SiC ICs, active and passive devices, and specialty features such as statistical model, noise model and aging model.
To support SoC designs with stringent turnaround time requirement, we offer a suite of foundation IPs including standard cell and IO libraries, embedded memory compilers, clock generators and other analog blocks.
